1. Field of the Invention
The present invention generally relates to computer systems generally, and, more particularly, to a novel implementation of a system and method for performing debugging operations of digital chips implemented in computer systems that is subject to software or hardware failures.
2. Description of the Prior Art
While bringing up an electronic system, the root cause for any given bug needs to be determined. In some cases, it is very hard to determine whether the hardware or the software is at fault. If the suspicion is on the hardware (or on very subtle interactions between the software and the hardware), conventional methods of debugging use probes external to the chips (such as oscilloscopes or logic analyzers). These probes give only a limited view of the state internal to the chips. To get a better view of the logical state and its evolution in time, several prior microprocessor designs have invested chip area in trace arrays. This additional chip area for trace arrays is useful in chip bring-up and debug, but adds cost to every production chip, where the trace array goes unused. While a definite improvement over external probing by logic analyzers, trace arrays still only give a limited view of the internal state of the microprocessor. This limitation stems both from the limited set of pre-selected on-chip signals that can be routed to the trace array (as determined and fixed at design time), and from the limited depth of any hardware-implemented array, so that the selected signals can be followed only for a limited length of time.
It would be highly desirable to provide a system and method for facilitating the debugging of various IC chips, by allowing the user to construct a cycle-by-cycle view of a very large part of the state of a digital chip, without design-imposed limitations on signal selection, and at a minimal overhead in chip area and cost.
Further desirable would be to provide a system and method for facilitating the debugging of various IC chips, by allowing the user to construct a cycle-by-cycle view of a very large part of the state of a digital chip that are under control of software.